Vol. 4, Issue 1 (2019)
Improving the performance of dadda multiplier using higher order compressors
Author(s): Julie Antony Roselin J, Augusta Angel M, Sujitha A
Abstract: In this paper, For high performance digital systems, high speed multiplication is the primary requirement. Multiplier plays vital role in order to perform the arithmetic operations in both digital signal processors and microprocessors. Several adder and multiplier designs have been proposed for implementations in exact computing. In this paper, different compressors such as 5:2, 6:2, 7:2 and 8:2 compressors are used for partial product reduction in a dadda multiplier is analyzed and designed. Dadda multiplier is a hardware multiplier and it requires fewer gates. It is more efficient compared to other multipliers. These designs rely on different features of compression such as precision in computation. It is also used to reduce the error rate and provides significant performance improvement compared to an existing methods with respect to delay, number of gates and power consumption.